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Posted
Advanced EOTS being planned for F-35 upgrade (block 4)

 

http://www.airrecognition.com/index.php?option=com_content&task=view&id=2047

It's quite telling that simply strapping this single thing on one of the 4.5 gen fighters that are supposed to be "a perfect match for if not better than F-35" would effectively double their combat potential :music_whistling:

Posted

 

Lol, my take away from what Bluto said is that the F-35 is no where near as capable as the A-10 in the CAS without him actually coming out and saying it!

Posted
Lol, my take away from what Bluto said is that the F-35 is no where near as capable as the A-10 in the CAS without him actually coming out and saying it!

 

I'm not a fan of the F-35, but what are you smoking. He said that the plane doesn't have the full software uploads. But it will by 2021. That it gathers all the situational information faster that any other aircraft. The plane is in operational testing, I'm sure the A-10 wasn't up to pare when it was in operational testing phase. Like he said collect all the facts before making stupid comments.

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Lt. Commander Jason "Punisher" M

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  • 2 weeks later...
Posted

Thanks badboom! Nice vid! That IS a beautiful bird. What I wouldn't give to be an AT or AE on the deck working with it.. or better yet a pilot flying it off the deck. It's going to be just like the F-14.. people will bash the hell out of it.. until it's in it's first action where it cleans up OPFOR that is. Then everyone's going to have a poster.. and Tom Cruise's grandson will be flying it in a Top Gun remake LOL

It's a good thing that this is Early Access and we've all volunteered to help test and enhance this work in progress... despite the frustrations inherent in the task with even the simplest of software... otherwise people might not understand that this incredibly complex unfinished module is unfinished. /light-hearted sarcasm

Posted
Thanks badboom! Nice vid! That IS a beautiful bird. What I wouldn't give to be an AT or AE on the deck working with it.. or better yet a pilot flying it off the deck. It's going to be just like the F-14.. people will bash the hell out of it.. until it's in it's first action where it cleans up OPFOR that is. Then everyone's going to have a poster.. and Tom Cruise's grandson will be flying it in a Top Gun remake LOL

! She's a beautiful machine
Posted
Thanks badboom! Nice vid! That IS a beautiful bird. What I wouldn't give to be an AT or AE on the deck working with it.. or better yet a pilot flying it off the deck. It's going to be just like the F-14.. people will bash the hell out of it.. until it's in it's first action where it cleans up OPFOR that is. Then everyone's going to have a poster.. and Tom Cruise's grandson will be flying it in a Top Gun remake LOL

Wouldn't a Top Gun remake be boring as hell with today's technology?

Posted

 

This would effect 1% of the possible F-35 pilots.....everyone else would be an average sized or larger human of 160lbs or more. The helmet would make all the pilots have thick fullback necks so it shouldn't be as big an issue as is being made of it.

VF-2 Bounty Hunters

 

https://www.csg-1.com/

DCS F-14 Pilot/RIO Discord:

https://discord.gg/6bbthxk

Posted (edited)

So I think I figured out the ICP specifications.

 

http://www.aviationtoday.com/av/military/JSF-Integrated-Avionics-Par-Excellence_1067.html#.ViztOrfhCUk

 

Core Processor

Hosting the mission systems software is the JSF's electronic brain, the ICP. Packaged in two racks, with 23 and eight slots, respectively, this computer consolidates functions previously managed by separate mission and weapons computers, and dedicated signal processors. At initial operational capability, the ICP data processors will crunch data at 40.8 billion operations/ sec (giga operations, or GOPS); the signal processors, at 75.6 billion floating point operations (gigaflops, or GFLOPS); and the image processors at 225.6 billion multiply/accumulate operations, or GMACS, a specialized signal processing measure, reports Chuck Wilcox, Lockheed's ICP team lead. The design includes 22 modules of seven types:

 

Four general-purpose (GP) processing modules,

Two GPIO (input/output) modules,

Two signal processing (SP) modules,

Five SPIO modules,

Two image processor modules,

Two switch modules, and

Five power supply modules.

 

The ICP also will have� "pluggable growth" for eight more digital processing modules and an additional power supply, Wilcox adds. It uses commercial off-the-shelf (COTS) components, standardizing at this stage on Motorola G4 PowerPC microprocessors, which incorporate 128-bit AltiVec technology. The image processor uses commercial field programmable gate arrays (FPGAs) and the VHDL hardware description language to form a very specialized processing engine.The ICP employs the Green Hills Software Integrity commercial real-time operating system (RTOS) for data processing and Mercury Computer Systems' commercial Multi-computing OS (MCOS) for signal processing. Depending on processing trades still to be made in the program, the JSF also could use commercial RTOSs in sensor front ends to perform digital preprocessing, according to Baker. The display management computer and the CNI system also use the Integrity RTOS. COTS reduces development risk and� ensures an upgrade path, according to Ralph Lachenmaier, the program office's ICP and common components lead.

 

Tying the ICP modules together like a backplane bus and connecting the sensors, CNI and the displays to the ICP is the optical Fibre Channel network. Key to this interconnect are the two 32-port ICP switch modules. The 400-megabit/sec IEEE 1394B (Firewire) interconnect is used externally to link the ICP, display management computer and the CNI system to the vehicle management system.

Low-level processing will occur in the sensor systems, but most digital processing will occur in the ICP. The radar, for example, will have the smarts to generate waveforms and do analog-to-digital conversion. But the radar will send target range and bearing data to the ICP signal processor, which will generate a report for the data processor, responsible for data fusion. Radar data, fused with data from other onboard and offboard systems, then will be sent from the ICP to the display processor for presentation on the head-down and helmet-mounted displays.

 

http://embeddedstar.com/press/content/2004/2/embedded12722.html

 

Raytheon Selects RACE++ Multicomputers for F-35 Joint Strike Fighter

 

https://www.mrcy.com/products/boards/race_powerpc7448/

 

Fully compatible with RACE++ Series 66.66-MHz RACEway interconnect

Includes RACE++ Series MULTI® Integrated Development Environment (IDE) for application development and testing

6U Form Factor

MCJ6 motherboard and two daughtercards.

Each daughtercard with either two 1.06-GHz MPC7448 processors or two 1.267-GHz processors with AltiVec™ technology.

MCJ6 configurations with one PowerPC 7448 daughtercard and one RINOJ-F-2.5 are also available

9U Form Factor

Up to seven PowerPC 7448 daughtercards and one RINOJ-F-2.5 available

 

https://www.mrcy.com/products/boards/race_powerpc7448/

 

PowerPC 7448 Daughtercard

For 1.06-GHzRACEway ports: 2

Processor frequency: 1.06-GHz

Compute nodes: 2

Memory frequency: 133 MHz

DDR DRAM per CN: 512 MB or 1024

DDR DRAM per daughtercard: 1024 MB or 2048 MB

L2 cache frequency: 1.06-GHz (32 bytes wide)

L2 on-chip cache: 1024 KB per CN

For 1.267-GHz

RACEway ports: 2

Processor frequency: 1.267-GHz

Compute nodes: 2

Memory frequency: 133 MHz

DDR DRAM per CN: 512 MB or 1024 MB

DDR DRAM per daughtecard: 1024 MB or 2048 MB

L2 cache frequency: 1.267-GHz (32 bytes wide)

L2 on-chip cache: 1024 KB per CN

PowerPC 7448 Multicomputer

6U VME/RACE++ MCJ6 and 2 daughtercards*

For 1.06-GHzMaximum power consumption

512 MB per CN: 68W**

1024 MB per CN: 72W

For 1.267-GHz

Maximum power consumption

512 MB per CN: 72W

1024 MB per CN: 76W

 

http://www.freescale.com/files/32bit/doc/fact_sheet/MPC7448FACT.pdf

 

The MPC7448 processor features a

high-frequency superscalar e600 PowerPC

core*, capable of issuing four instructions per

clock cycle (three instructions plus one

branch) into

11 independent execution units:

> Four integer units (three simple plus one

complex)

> Double-precision floating point unit

> Four AltiVec technology units (simple,

complex, floating and permute)

> Load/store unit

> Branch processing unit

AltiVec Acceleration

The MPC7448 includes the same powerful

128-bit AltiVec vector execution unit as found

in previous MPC7xxx devices. AltiVec

technology may dramatically enhance the

performance of applications such as voiceover-Internet

Protocol (VoIP), speech

recognition, multi-channel modems, virtual

private network servers, high-resolution 3-D

graphics, motion video (MPEG-2, MPEG-4),

high fidelity audio (3-D audio, AC-3), and so

on. AltiVec computational instructions are

executed in the four independent, pipelined

AltiVec execution units. A maximum of two

AltiVec instructions can be issued in order to

any combination of AltiVec execution units per

clock cycle. In the MPC7448, a maximum of

two AltiVec instructions can be issued out-oforder

to any combination of AltiVec execution

units per clock cycle from the bottom two

AltiVec instruction queue entries. For example,

an instruction in queue one destined for

AltiVec integer unit one does not have to wait

for an instruction in queue zero that is stalled

behind an instruction waiting for operand

availability.

Edited by Emu
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