Beta 6 Coming Soon

[BrumTx]

Guys, Guys, Guys,

 

In the subject line it says "BETA 5 DELAY"

 

Lets stop this stupidity and get back to the subject matter in hand .........

 

PLEASE!!!!!!!!

[Gonzo01]

There is no "single cause" to the decrease in clock speeds in chips. There are quite a few compounding issues that have essentially stopped the increase in CPU clock frequencies.

 

1) Smaller die sizes do all sorts of weird things. I don't think ten years ago anyone would have seriously considered that optical lithography would take us down to (and below) the 45 nm technology node, which is actually below the wavelength of light. Leakage current (due to fun things like quantum tunneling) is making static power of a chip become more and more obvious. As a result, dynamic power needs to correspondingly decrease to keep chips from melting.

2) Designing at a faster clock is very expensive. CPU designers are used to using exotic architectures (domino logic, for instance) to account for faster clocks, but ASIC designers are not. Development for slower architectures (ie, the classic static CMOS) has become a bigger part of the pie than CPU architectures. Developments in the former tend to migrate to the latter.

3) It's rather difficult to get data off of devices at high data rates. Multigigabit serializers are taking over major data paths. Although this doesn't have an inherent impact on CPU speeds, it means that bus speeds are becoming less important.

4) Pipelining only gets you so far. It's already common to use a pipeline simply to account for propagation delays along a wire. There's no way to improve those propogation delays short of optical interconnects. We're already past the point of considering RC time constants of interconnects. It's more common to hear about characteristic impedance (traditionally an RF phenomenon) of interconnects.

5) Memory bandwidth hasn't kept up with CPU bandwidth. At the absolute far end (graphics DDR RAM), it is possible to get about 1 GHz out of memory. However, more commonly used PC memories are not nearly so fast. As a result, the net benefit of a higher clock frequency is mitigated by any direct memory interactions.

6) Faster CPUs require bigger caches (to ensure that number 5 doesn't become as big of an issue - you don't want a CPU to have to go out to memory to do anything when memory is several orders of magnitude slower than the CPU). Bigger caches are incredibly expensive in terms of die area. This is why server processors are quite a bit more expensive than consumer CPUs.

7) People are talking about architectural differences, but SCDB's got the right idea -- it's a quantum-mechanics-level limitation of the actual silicon. We have plenty of researchers capable of addressing the architectural issues, but they're not being funded because of known physical limits. If you're wondering why we can have 9 GHz ASICs but not equally fast CPUs, it's because CPUs require quite a bit of silicon real estate -- all on the same clock (mostly the cache). It's just too long a distance for signals to propagate (which, as an aside, is just one of the physical limits -- the other is transistor switching).

 

Broadly speaking it is a power issue. Chips today run at the absolute limit of power density; they generate just as much heat as the package is able to dissipate, and if the package could do better, you can be damn sure they would increase the power budget. You could make the chips go faster, but you'd have more power to get rid of. It's a classic engineering tradeoff. Is your engineering effort better spent on creating clever low-power tricks throughout the chip so you can run faster, or on creating more parallel circuits so you can do more in a clock cycle, with a slower clock? Complicate the equation by the unfortunate fact that your successful marketing to date is based on clock speed=performance (whoops), and by competitive pressures which mean performance has a time value, so that what's fast today is slow in a year, and it's a rather messy issue.

 

Around 2000 the equation flipped as we hit the power wall. The design mentality of a speed race - keep increasing the clock speed - no longer makes sense when you need 10x the engineering effort to double the clock speed as you do to double performance through parallelism.

 

I should also mention that while the transistors themselves are not close to their fundamental speed limit, the microprocessors contain large functional units that must complete all of their calculations within one clock cycle, and making these functional units fast enough can be quite a challenge, another source of the extra engineering effort that comes with increasing clock speed (or decreasing cycle time if you prefer). Timing margins shrink, race conditions are harder to deal with, etc. AMD has recently had trouble with the Translation Lookaside Buffer, and it is reported that the bug occurs only at higher clock frequencies. The RC interconnect delay comes into play here as well; wires are slow enough that you have to pay attention to their delay and put repeaters everywhere, another source of extra design effort.

 

Essentially, the problem is that as features on a chip are scaled down, the resistance increases inversely to the width of the interconnect wire. That is, the resistance goes up as the wire gets narrower. The capacitance of the wire decreases proportionally to the width of the wire. That is, the decreasing width decreases the capacitance. When you combine them as R * C, one increasing and the other decreasing proportionally, it means that the RC delay remains constant for a given length of wire even as you shrink it. The RC delay determines the time it takes a signal to propagate from one end of the wire to the other. What this all means is that while shrinking features tends to speed everything else up, for example transistor switching delays, the propagation delay across the connecting wires does not speed up.

 

So as you scale to smaller and smaller features, the dominant performance effect becomes the speed of interconnect wires, not the speed of transistors. The speed of the transistors becomes irrelevant. Your limitation is the interconnect. As you speed up the clock, the distance a signal can travel and the number of transistors you can reach in one clock period goes down.

 

One thing you can do about it is to make fatter wires, but that becomes self-defeating as the wires take up more die space and cause the transistors to be farther apart, increasing interconnect distances. Another solution is the use of low-K materials for the insulators in place of silicon oxide. Low-K materials have a lower dielectric constant which reduces the capacitance. But ultimately, you reach a limit at which you can clock a chip and still get signals from one edge to the other in one clock cycle.

Edited January 15, 2011 by Gonzo01

[Spadje]

Spadje don't believe everything you hear unless you can verify it yourself. I'm am not saying your wrong, I'm just saying be careful what you put out their based on your own understanding.

 

hahahahahahaha.... Man I love people on the internet.....:lol::doh: Please go to http://www.futuremark.com and tell these guys what they are doing is impossible...also hit up http://www.hardocp.com and let them know too....

 

Woot back on topic cannot wait for beta 5

 

Spadje

 

EDIT: Also what you stated above is a quote from here http://ask.metafilter.com/78227/Why-did-CPUs-stop-getting-faster-about-5-years-ago and that was a 5 year old topic stating "ntel also said the chips will be built using its new manufacturing process that involves shrinking parts of the chips down to 45 nanometres, or billionths of a metre, from the 65-nanometre process the company uses now." which they are already doing and have been for about 2 years now. That is an OLD article on why they stopped speeding up 5 years ago!!!!

Edited January 16, 2011 by Spadje

[TwoLate]

hahahahahahaha.... Man I love people on the internet.....:lol::doh: Please go to http://www.futuremark.com and tell these guys what they are doing is impossible...also hit up http://www.hardocp.com and let them know too....

 

Woot back on topic cannot wait for beta 5

 

Spadje

 

If you think those ovc machines are typical you are in a fantasy world. Even if you can ovc to 5 ghz or over with liquid cool you will not have a dependable machine. Getting default ghz to 5.0 will not happen on silicon. Try running a sim at those speeds everyday.

[Gonzo01]

hahahahahahaha.... Man I love people on the internet.....:lol::doh: Please go to www.futuremark.com and tell these guys what they are doing is impossible...also hit up www.hardocp.com and let them know too....

 

Woot back on topic cannot wait for beta 5

 

Spadje

 

Spadje maybe you should re-read my post. This is not about hitting 5 Ghz, it's about coming to the limits of what Silicon can be used for in a processor chip. I am trying to help you and in the process educate you. By the way, you of all people should know that Futuremark is about getting the fastest FPS at whatever cost, and it is not about stability or longevity of the chip. Most of these people use Liquid Nitrogen as a coolant for what, a whole 13 seconds.

 

It also might suprise you to know my background before you start questioning everything I say.

 

I think it's fair at best that both of us agree to disagree and lets close this topic.

 

 

Best Regards,

Gonzo

Edited January 16, 2011 by Gonzo01

[Spadje]

Sorry back to the actual subject of this thread. Did not mean to hijack. Have a great weekend everyone

Edited January 16, 2011 by Spadje

[VMFA117_Poko]

Anyone can share some light how many betas are planned?

[Squid_DK]

I'm fairly certain that there isn't any fixed number, you keep tweaking and modifying until the product is stable and within the set parameters. public could be anything from one to a billion more (excaggerating here on purpose) I dare not guess at what version the closed beta is on but I have a faint idea that it isn't in single digits.

 

Staffan

Edited January 17, 2011 by Danish_Squid
Spelling

[Dejjvid]

ED will release the RC when all bugs are sorted, or the not working feature is removed.

And if everything is ok with the RC. It will go gold. But i think we'll see RC2 before final. That often tend to happen in SW development.

[G00dnight]

ok whose spreading malicious rumours of beta releases being planned..:megalol:

[VMFA117_Poko]

ok whose spreading malicious rumours of beta releases being planned..:megalol:

I dont know nothing about that... :smilewink:

[sweinhart3]

Spadje maybe you should re-read my post. This is not about hitting 5 Ghz, it's about coming to the limits of what Silicon can be used for in a processor chip. I am trying to help you and in the process educate you. By the way, you of all people should know that Futuremark is about getting the fastest FPS at whatever cost, and it is not about stability or longevity of the chip. Most of these people use Liquid Nitrogen as a coolant for what, a whole 13 seconds.

 

It also might suprise you to know my background before you start questioning everything I say.

 

I think it's fair at best that both of us agree to disagree and lets close this topic.

 

Best Regards,

Gonzo

 

I forgot where I read it but Ive read a couple times that Intel has found a replacement for silicon that will allow them to move beyond the limits of silicon. This of course is still in the research phase though. They have also demonstrated optical transmition on silicon that will largely elliminate much of the problems you have described here with interconnects. The article may be old but the physics still apply. Fortunately, Intel has the kind of budgets to research and develop alternatitves that will enable Moores Law to continue many years down the road. Im lucky enough to be getting ahold of a free engineering sample of the i7 990x cpu in a week or two.

[skypirate]

free engineering sample of the i7 990x cpu in a week or two.

 

Mate, you would be so kind to report how's the performance with the A-10 sim having the 990x rigged up, will ya'....

[Mustang]

I've just had a read through Wags' latest update regarding Beta 5 changes

 

http://forums.eagle.ru/showthread.php?t=66136

 

WOW! just about everything i can think of is covered in this upcoming beta, i cannot wait to try it out! :thumbup:

 

Great work ED, and great work ED Testers :)

Edited January 20, 2011 by Mustang

[clearjet1]

I for one cannot wait unti the Oxygen test doesn't cause the needle to go below 0 and zoom around ccw... ~grin~

[sobek]

I for one cannot wait unti the Oxygen test doesn't cause the needle to go below 0 and zoom around ccw... ~grin~

 

I can't tell if you're being sarcastic, so here goes: That's the way it works in the real thing. ;)

[Raz_Specter]

wow some great things fixed :) looking forward to the realease - thanks

[tdar]

a quick question regarding Wags' post: CBU-103/105's have been updated, but does the A-10C even carry them in Beta 4? I thought what we had were the non-WCMD CBU-87/97s, which caused a game crash anyways?

 

edit: just noticed item #3 in Wags' post suggests the HOF issue which caused the CBU failure has been fixed, so I assume the CBUs work; And I also noticed that the 103's and the 105's were always there!

Edited January 20, 2011 by tdar

[Steel Jaw]

Dropping CBUs in the beta 4 drops causes CTDs.

[BrumTx]

Looking good ED and Wags ............. thanks for all your hard work :):) :joystick::pilotfly:

[Gonzo01]

My money is on the stability of the Mission Builder and Radio Comms. I'll be happy when the AWACS stops referring to himself as Enfield.

[Steel Jaw]

Online

Refueling

Please

.

[BrumTx]

Online

Refueling

Please

.

 

 

For A1 as well, with the boom actually dropping down, instead of staying up ... at the moment

[Steel Jaw]

with the boom actually dropping down, instead of staying up

 

No kidding: I cant get the condom on it that way... :D

[BrumTx]

No kidding: I cant get the condom on it that way... :D

 

Mower, my Wife is rolling on the floor from you last comment .... great stuff lol :thumbup: